module x74ls161(
    input CL_n,
    input CP,
    input [3:0]A,
    input EP,
    input ET,
    input LD_n,
    output reg[3:0]Q,
    output RCO
    );

always@(posedge CP or negedge CL_n)
if(~CL_n) begin
    Q<=4'b0000;
end
else
    if(~LD_n) begin
        Q=A;
    end
    else begin
         if(EP&ET) begin
            Q=Q+1'b1;
         end
         else
            Q=Q;
end
assign RCO=(Q==4'b1111);          
endmodule
